Researchers from Meta and semiconductor startup Panmnesia have outlined a Compute Express Link (CXL) architecture designed to extend tightly coupled AI computing beyond a single rack. The work appears in a review in Nature Reviews Electrical Engineering published in August.
The proposed design brings CPUs, accelerators and memory into a larger CXL-based coherence domain, with the goal of reducing the latency variation that grows as AI jobs span more servers and racks.
Extending the scale-up domain
Today, accelerators within a rack can communicate through high-speed scale-up interconnects, while traffic that leaves the rack usually moves over scale-out networks such as Ethernet or InfiniBand. The review argues that this boundary introduces additional software and networking overhead, making latency less predictable as systems scale.
The architecture combines CXL with a high-fan-out non-blocking switch, a link acceleration unit and a fabric controller. The authors also describe a hierarchical deployment model intended to keep communication paths more regular as resources are spread across racks and pods.
Panmnesia’s release says the architecture can place as many as about 960 accelerators in one coherence domain under the configuration described in the review. It also reports cross-server access latency in the several-hundred-nanosecond range, compared with microsecond-level access for conventional network-based infrastructure. Those figures are architectural comparisons presented by the authors and should not be read as independent benchmarking of every deployment.
CXL over optics for longer reach
Electrical signaling imposes a physical limit on how far a CXL fabric can extend at high data rates. The review therefore considers CXL-over-optics as a way to carry the same fabric across longer distances while preserving the overall architecture.
Panmnesia said it has implemented core components in silicon. The company said its CXL/PCIe fabric controller and link acceleration unit have completed silicon validation, while a fabric switch has been fabricated and pre-release silicon is being supplied.
The proposal arrives as AI infrastructure vendors increasingly treat power, cooling and interconnects as one system-level problem. TNGlobal earlier reported on Foxconn and Schneider Electric developing integrated AI data center reference architectures covering compute, power and cooling.
The Meta-Panmnesia work remains a proposed architectural direction rather than a deployed industry standard. Its significance is in showing how CXL could be pushed from component-level memory expansion toward a broader scale-up fabric for distributed AI systems.
South Korean AI chip firm Panmnesia raises $12.5M in seed funding with a valuation exceeding $81.4M