ASML and Taiwan Semiconductor Manufacturing Company (TSMC) have formed an industry initiative to develop 12-inch photomasks for High Numerical Aperture extreme-ultraviolet lithography, aiming to make the advanced chipmaking systems more productive for large and complex designs.
The companies said on September 8 that the initiative targets a 12-inch mask pilot line in 2031 and full lithography-system readiness for advanced-node production in 2033. Samsung Electronics separately said it will join the effort, while other chipmakers and suppliers have expressed interest.
Larger masks address a High NA constraint
Photomasks carry the patterns that lithography systems project onto silicon wafers. ASML’s current High NA EUV tools will initially enter production with the industry’s established 6-inch masks, according to the joint announcement.
High NA systems use optics with a higher numerical aperture to print finer features than earlier EUV machines. The trade-off is a smaller exposure field when used with current masks, which can require manufacturers to stitch together multiple exposures for especially large chips. ASML and TSMC said a move to 12-inch masks is intended to remove that constraint, improve scanner productivity and reduce manufacturing costs.
The change would require coordination across mask blanks, patterning, inspection, cleaning, transport and lithography equipment. That explains the long timetable: the partners are seeking an industry-wide transition rather than a proprietary format used by one chipmaker.
The larger format is not a prerequisite for the first High NA production. Chipmakers plan to begin with 6-inch masks and potentially adopt 12-inch masks later, meaning the initiative is a second-stage productivity roadmap rather than a delay to the technology’s initial deployment.
Asian chipmakers outline adoption plans
TSMC said it intends to use ASML’s High NA technology in high-volume manufacturing for advanced logic nodes beginning in 2030. It expects the number of layers requiring High NA exposure to increase as transistor architectures become more complex, particularly for chips supporting AI workloads.
Samsung said in its own announcement that it plans to use High NA EUV for high-volume DRAM manufacturing from 2028 and will participate in the large-format-mask initiative. Reuters reported that South Korea’s SK Hynix is evaluating participation and is also targeting High NA use in DRAM mass production in 2028.
Intel has already installed High NA systems and is using the technology for some production work, Reuters reported, but widespread high-volume adoption at TSMC and the South Korean memory manufacturers has yet to begin.
The different starting dates reflect separate roadmaps for logic and memory. They should not be read as a single industry deadline, and the companies have not specified how many production layers will initially use High NA or when the larger masks would replace today’s format.
Productivity gain remains a projection
ASML Chief Technology Officer Marco Pieters told Reuters that system productivity could rise by about 40 percent if the larger-mask transition succeeds. That is a forward-looking estimate rather than a measured result from a production-ready 12-inch line.
The companies did not disclose the investment required, which suppliers have formally committed, or how the costs of converting mask infrastructure would be shared. The 2031 pilot and 2033 system-readiness targets also extend beyond the first planned use of High NA with existing masks.
The initiative matters to Asia because TSMC, Samsung and SK Hynix sit at the center of advanced logic and memory production. Larger masks could help them use High NA systems for chips whose physical dimensions and complexity would otherwise make stitching more difficult, including data-center accelerators and high-bandwidth-memory-related designs.
For now, the announcement establishes a technical roadmap and a coalition-building process. Delivering the projected benefits will depend on the wider mask ecosystem producing and qualifying new equipment well before chipmakers need the format at commercial scale.
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